1. Field of the Invention
The invention relates to a method of fabricating an interpoly dielectric layer of embedded dynamic random access memory (Embedded DRAM), and more particularly to a method of fabricating an interpoly dielectric layer of embedded dynamic random access memory which can improve thermal stability of a titanium silicide layer.
2. Description of the Related Art
Dynamic random access memory is a kind of volatile memory and digital signal is determined by charge or discharge of a DRAM charge storage capacitor. Therefore, the data stored in the memory cell disappears completely when no power is supplied to the DRAM. The memory cell of a DRAM includes a field effect transistor (FET) and a capacitor. The capacitor is used for data storage in a DRAM memory cell. If more charges can be stored in the capacitor, the effect of disturbance becomes lower as the data storage is read by an amplifier.
Generally, logic devices include an inverter, an AND gate, an OR gate, a NAND gate and a NOR gate. A MOS transistor acts as a switch for operation of a logic device and either a logic one as "on" or zero as "off" is controlled by the gate of the MOS transistor.
The embedded DRAM of prior art comprises an embedded DRAM region and a logic circuit region. Referring to FIG. 1, device isolation structure 102 is formed on the substrate 100. An active region 104 having gate electrode 108 and wiring lines 110 and a logic device region 106 are then defined. The structure of gate electrode 108 is almost the same as that of the wiring lines 110. The major difference between the gate electrode 108 and the wiring lines 110 is that the gate electrode 108 and the substrate 100 are separated by the gate oxide layer 112 and the wiring line 110 is formed on the device isolation structure 102. The formation of capping oxide layer 116 protects the polysilicon layer 114. Capping oxide layer 116 is formed on the gate electrode 108 and the wiring lines 110 and oxide spacer 118 is formed on the either side of gate electrode 108 and wiring lines 110. Source/drain regions 120 are typically provided on either side of the gate electrode 108 to complete the transfer field effect transistor (FETs). An oxide layer 122 is formed on the substrate 100 and a lower capacitor electrode 124, a dielectric layer 126 and an upper capacitor electrode 128 are formed on the substrate 100 respectively.
The logic FET 130 is formed on the gate oxide layer 132 and the logic FET also includes the polysilicon gate electrode 134. A capping oxide layer 136 is still formed on the polysilicon gate electrode 134 and the oxide spacer 138 is formed to maintain the source/drain extension. Source/drain regions 120 are formed on the sides of the gate electrode 134 and a self-aligned salicide process is performed to form a titanium silicide layer 140 on the surface of source/drain region 120.
A planarization process is usually performed to the substrate 100 as the embedded DRAM is fabricated. BPSG 142, formed by chemical vapor deposition (CVD), is used to planarize the substrate 100. BPSG is a silicon oxide with some boron and phosphorus incorporated. In order to prevent boron and phosphorus from diffusing into source/drain region 120 during subsequent thermal process, it is necessary to use atmosphere pressure CVD (APCVD) to form an oxide layer 144 on the substrate 100 prior to the formation of BPSG.
Oxide/nitride/oxide (ONO) is always used as a dielectric layer 126 of capacitor in the current technologh when the embedded DRAM is fabricated. A furnace thermal process is necessary as the ONO is used as a dielectric layer. The thermal process described above exposes the chip to a high temperature. So the integrity of silicide 140 degrades as the high temperature process is performed and agglomeration of silicide in the logic circuit region 106 is produced at the interface of source/drain region 120 and the oxide layer 142, as shown in FIG. 2. The quality and the performance of devices are therefore affected.
In addition, the APCVD oxide layer 142 formed on the surface of the substrate 100 increases the contact aspect ratio. The contact etching process becomes more difficult.